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Survey of various Techniques to Reduce Leakage Power in FPGA

S.Poovarasan R.Brindha.

Abstract
FPGA is known as Field Programmable Gate Array that can be programmed in the field after manufacture. It can be reprogrammed to desired application or functionality requirements after manufacturing. The major difference between FPGA and Application Specific Integrated Circuits (ASICs), which are custom manufactured for specific design tasks. Due to their programmable nature, FPGAs are an ideal fit for many different markets. As the industry leader, Xilinx provides comprehensive solutions consisting of FPGA devices, advanced software, and configurable, ready-to-use IP cores for markets and applications. However, the power consumption of FPGAs remains prohibitive for some applications. Power dissipation and Leakage power is the major issue of FPGAs. Thus, low-leakage FPGAs are essential if they are to be used for hand-held applications. Some more techniques are discussed here to reduce power dissipation. Power gating and Clock gating techniques are more efficient for leakage power reduction

Key words: Field Programmable Gate Arrays, Leakage power, Power gating, Clock gating


 
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Pubmed Style

S.Poovarasan R.Brindha. Survey of various Techniques to Reduce Leakage Power in FPGA. . 2016; 4(1): 23-28. doi:10.31838/ijccts/04.01.04


Web Style

S.Poovarasan R.Brindha. Survey of various Techniques to Reduce Leakage Power in FPGA. http://www.ijccts.org/?mno=302643848 [Access: June 12, 2021]. doi:10.31838/ijccts/04.01.04


AMA (American Medical Association) Style

S.Poovarasan R.Brindha. Survey of various Techniques to Reduce Leakage Power in FPGA. . 2016; 4(1): 23-28. doi:10.31838/ijccts/04.01.04



Vancouver/ICMJE Style

S.Poovarasan R.Brindha. Survey of various Techniques to Reduce Leakage Power in FPGA. . (2016), [cited June 12, 2021]; 4(1): 23-28. doi:10.31838/ijccts/04.01.04



Harvard Style

S.Poovarasan R.Brindha (2016) Survey of various Techniques to Reduce Leakage Power in FPGA. , 4 (1), 23-28. doi:10.31838/ijccts/04.01.04



Turabian Style

S.Poovarasan R.Brindha. 2016. Survey of various Techniques to Reduce Leakage Power in FPGA. International Journal of Communication and Computer Technologies, 4 (1), 23-28. doi:10.31838/ijccts/04.01.04



Chicago Style

S.Poovarasan R.Brindha. "Survey of various Techniques to Reduce Leakage Power in FPGA." International Journal of Communication and Computer Technologies 4 (2016), 23-28. doi:10.31838/ijccts/04.01.04



MLA (The Modern Language Association) Style

S.Poovarasan R.Brindha. "Survey of various Techniques to Reduce Leakage Power in FPGA." International Journal of Communication and Computer Technologies 4.1 (2016), 23-28. Print. doi:10.31838/ijccts/04.01.04



APA (American Psychological Association) Style

S.Poovarasan R.Brindha (2016) Survey of various Techniques to Reduce Leakage Power in FPGA. International Journal of Communication and Computer Technologies, 4 (1), 23-28. doi:10.31838/ijccts/04.01.04