A LOW POWER EFFICIENT DESIGN OF FULL ADDER USING TRANSMISSION GATES

Authors

  • P.Alagu Pandian
  • K. Sakthivel
  • K.Sheik Alavudeen
  • R.Lakshmi Priya

Keywords:

Pass Transistor Logic (PTL), Power-Delay Product (PDP), Transmission gate (TG), Electronic Design Automation (EDA)

Abstract

A Full adder circuit is a very important component of the design of integrated circuits in VLSI design. In this paper represents a full adder using transmission gates at supply voltage is 1.8 dc voltages. The result of the post layout simulation (using CADENCE EDA TOOL) have been compare with the results of similar previously reported for adder circuits. In this proposed transmission gate circuits is very high efficient in terms of power, delay and area consumption compare too many other full adder circuits. 

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Published

2023-05-20

How to Cite

Pandian, P., Sakthivel, K., Alavudeen, K., & Priya, R. (2023). A LOW POWER EFFICIENT DESIGN OF FULL ADDER USING TRANSMISSION GATES. International Journal of Communication and Computer Technologies, 5(1), 1–5. Retrieved from https://ijccts.org/index.php/pub/article/view/45

Issue

Vol. 5 No. 1 (2017)

Section

Research Article

License

Copyright (c) 2023 International Journal of communication and computer Technologies

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