Advanced Transistor Nodes: Basic module realization for data security

Authors

  • A. FRATKIN Department of Electrical and Computer Engineering, Ben-Gurion University, Beer Sheva, Israel
  • F. KAIDANOV Department of Electrical and Computer Engineering, Ben-Gurion University, Beer Sheva, Israel
  • W. SCHAPIRA Department of Electrical and Computer Engineering, Ben-Gurion University, Beer Sheva, Israel
  • G. SHAVIV Department of Electrical and Computer Engineering, Ben-Gurion University, Beer Sheva, Israel

Keywords:

Body Biasing, Decoder, FinFET, Source Biasing

Abstract

In this research paper, we planned a low leakage power and high speed decoder for memory cluster application and proposed modern four strategies. In this paper, the collation of source predisposition decoder, source coupling decoder, body bias decoder and cluster decoder are planned and analyzed for memory cluster application. The plan is recreated utilizing Cadence virtuoso with 20nm innovation. The parameters of 3 to 8 decoders designed at 20 nm FinFET nodes using Cadence Virtuoso.

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Published

2023-05-20

How to Cite

FRATKIN, A., KAIDANOV, F., SCHAPIRA, W., & SHAVIV, G. (2023). Advanced Transistor Nodes: Basic module realization for data security. International Journal of Communication and Computer Technologies, 11(1), 61–67. Retrieved from https://ijccts.org/index.php/pub/article/view/171

Issue

Vol. 11 No. 1 (2023)

Section

Research Article

License

Copyright (c) 2023 International Journal of communication and computer Technologies

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