State of art design of novel adder modules for future computing
Keywords:Adders, pass logic implementations, logic devices, low- power, power delay product, layout design
This paper presents power analysis of the seven full adder cells reported as having a low PDP (Power Delay Product), by means of speed, power consumption and area. These full adders were designed upon various logic styles to derive the sum and carry outputs. All these full adders designed using TDK 90 nm Technology and simulated using mentor graphics EDA tool with BSIMv3 (model 49). And the layouts of all these full adders designed in Icstation of Mentor Graphics.
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