State of art design of novel adder modules for future computing

Authors

  • ALI MOHAMMADZADEH New Sciences and Technologies Department, Tehran University, Tehran 1417466191, Iran
  • B. J. ADAMS New Sciences and Technologies Department, Tehran University, Tehran 1417466191, Iran

Keywords:

Adders, pass logic implementations, logic devices, low- power, power delay product, layout design

Abstract

This paper presents power analysis of the seven full adder cells reported as having a low PDP (Power Delay Product), by means of speed, power consumption and area. These full adders were designed upon various logic styles to derive the sum and carry outputs. All these full adders designed using TDK 90 nm Technology and simulated using mentor graphics EDA tool with BSIMv3 (model 49). And the layouts of all these full adders designed in Icstation of Mentor Graphics.

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Published

2023-05-20

How to Cite

MOHAMMADZADEH, A., & ADAMS, B. J. (2023). State of art design of novel adder modules for future computing. International Journal of Communication and Computer Technologies, 11(2), 53–67. Retrieved from https://ijccts.org/index.php/pub/article/view/159

Issue

Vol. 11 No. 2 (2023)

Section

Research Article

License

Copyright (c) 2023 International Journal of communication and computer Technologies

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