SYMMETRIC STACKING BINARY COUNTER

Abstract

High efficient and fast addition of multiple operands is an essential process in any computational units. The power and speed efficiency of multiplier circuits is one of critical importance in the overall performance of microcontrollers and microprocessors. Multiplier circuits are an essential part of an arithmetic logic unit, or a digital signal processor system for performing convolution, image processing, filtering, and other purposes. The binary multiplication of fixedpoint numbers and integers ends up in partial products that is used to provide the ultimate product. Adding those partial products dominates the power consumption and efficiency of the number. A new binary counter design uses 3- bit stacking circuit, which groups all the “1” bits together, to combine pairs of 3- bit stacks into 6- bit stacks through novel symmetric method has been proposed. The bit stacks square measure then reborn to binary counts, producing 6:3 counter circuits with no xor gates on the critical path. This avoidance of xor gates results in faster designs with efficient area and power utilization. Additionally, using the counters present in proposed system in existing counter - based Wallace tree multiplier architectures reduces latency and power consumption for 128 and 64 - bit multipliers. We apply this Counter design in FIR filter Application