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A LOW POWER EFFICIENT DESIGN OF FULL ADDER USING TRANSMISSION GATES

P.Alagu Pandian K.Sakthivel K.Sheik Alavudeen R.Lakshmi Priya.

Abstract
A Full adder circuit is a very important component of the design of integrated circuits in VLSI design. In this paper represents a full adder using transmission gates at supply voltage is 1.8 dc voltages. The result of the post layout simulation (using CADENCE EDA TOOL) have been compare with the results of similar previously reported for adder circuits. In this proposed transmission gate circuits is very high efficient in terms of power, delay and area consumption compare too many other full adder circuits.

Key words: Pass Transistor Logic (PTL), Power-Delay Product (PDP), and Transmission gate (TG), Electronic Design Automation (EDA). I


 
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Pubmed Style

P.Alagu Pandian K.Sakthivel K.Sheik Alavudeen R.Lakshmi Priya. A LOW POWER EFFICIENT DESIGN OF FULL ADDER USING TRANSMISSION GATES. . 2017; 5(1): 01-05. doi:10.31838/ijccts/05.01.01


Web Style

P.Alagu Pandian K.Sakthivel K.Sheik Alavudeen R.Lakshmi Priya. A LOW POWER EFFICIENT DESIGN OF FULL ADDER USING TRANSMISSION GATES. http://www.ijccts.org/?mno=302643801 [Access: October 07, 2020]. doi:10.31838/ijccts/05.01.01


AMA (American Medical Association) Style

P.Alagu Pandian K.Sakthivel K.Sheik Alavudeen R.Lakshmi Priya. A LOW POWER EFFICIENT DESIGN OF FULL ADDER USING TRANSMISSION GATES. . 2017; 5(1): 01-05. doi:10.31838/ijccts/05.01.01



Vancouver/ICMJE Style

P.Alagu Pandian K.Sakthivel K.Sheik Alavudeen R.Lakshmi Priya. A LOW POWER EFFICIENT DESIGN OF FULL ADDER USING TRANSMISSION GATES. . (2017), [cited October 07, 2020]; 5(1): 01-05. doi:10.31838/ijccts/05.01.01



Harvard Style

P.Alagu Pandian K.Sakthivel K.Sheik Alavudeen R.Lakshmi Priya (2017) A LOW POWER EFFICIENT DESIGN OF FULL ADDER USING TRANSMISSION GATES. , 5 (1), 01-05. doi:10.31838/ijccts/05.01.01



Turabian Style

P.Alagu Pandian K.Sakthivel K.Sheik Alavudeen R.Lakshmi Priya. 2017. A LOW POWER EFFICIENT DESIGN OF FULL ADDER USING TRANSMISSION GATES. International Journal of Communication and Computer Technologies, 5 (1), 01-05. doi:10.31838/ijccts/05.01.01



Chicago Style

P.Alagu Pandian K.Sakthivel K.Sheik Alavudeen R.Lakshmi Priya. "A LOW POWER EFFICIENT DESIGN OF FULL ADDER USING TRANSMISSION GATES." International Journal of Communication and Computer Technologies 5 (2017), 01-05. doi:10.31838/ijccts/05.01.01



MLA (The Modern Language Association) Style

P.Alagu Pandian K.Sakthivel K.Sheik Alavudeen R.Lakshmi Priya. "A LOW POWER EFFICIENT DESIGN OF FULL ADDER USING TRANSMISSION GATES." International Journal of Communication and Computer Technologies 5.1 (2017), 01-05. Print. doi:10.31838/ijccts/05.01.01



APA (American Psychological Association) Style

P.Alagu Pandian K.Sakthivel K.Sheik Alavudeen R.Lakshmi Priya (2017) A LOW POWER EFFICIENT DESIGN OF FULL ADDER USING TRANSMISSION GATES. International Journal of Communication and Computer Technologies, 5 (1), 01-05. doi:10.31838/ijccts/05.01.01




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